An SR latch is a basic memory element that can store one bit of information. It has two inputs and two outputs:
S (Set): Sets the output Q to 1.
R (Reset): Resets the output Q to 0.
The latch has two outputs:
Q: Represents the stored bit.
Q': The complement of Q.
The basic implementation of an SR latch using AND, OR and NOT is presented. Let's break it down step by step to understand how it works as an SR latch.
+-----------------+
| |
+-\ \ |
)OR)--+ Y |
S --/ / | |
| |
+-| \ |
|\ |AND)--+-- Q
R -----| O---| /
|/ Z
The circuit consists of:
An OR gate for the Set (S) input.
A NOT gate to complement the Reset (R) input.
An AND gate for inverted Reset (R) input.
There is a feedback connection from the output Q to the input of the OR gate.
Here is the stepwise demo of how the SR latch circuit works:
Assume the initial state is Q = 0. (We can equally suppose Q = 1).
S = 1 is applied to the OR gate.
The OR gate output Y is 1, since OR gate output is 1 if any of the inputs is 1.
R = 0 is applied to NOT gate input. Its output Z is 1.
Both inputs of AND gate are 1 so its output Q is set to 1.
This is the set operation and Q is set to 1.
When both S = 0 and R = 0, the circuit maintains its previous state.
The OR gate output stays at 1.
Both AND gate inputs are 1 and its output Q stays at 1.
The feedback connection ensure that the outputs Q does not change in hold state.
This is the hold operation.
R = 1 is applied to the AND gate.
The NOT gate output Z is 0.
The AND gate output is 0, since one of its inputs is 0.
This 0 becomes the new value of Q.
The feedback ensures that Q = 0 is stable until the inputs change.
This is the reset operation
With both S = 0 and R = 0, the circuit maintains its current state.
The feedback connections ensure that the outputs Q remain 0.
If both S = 1 and R = 1 are applied simultaneously, the circuit enters an illegal state.
The OR gate outputs 1, and the AND gate outputs 0. However, this state is not permitted.
Applying Set and Reset at the same time does not make sense.
This state is undefined and should be avoided.
+-------+--+--+-------+
|Q prev |S |R |Q next |
+-------+--+--+-------+
| 0 |0 |0 | 0 |
| 0 |0 |1 | 0 |
| 0 |1 |0 | 1 |
| 0 |1 |1 | X |
| 1 |0 |0 | 1 |
| 1 |0 |1 | 0 |
| 1 |1 |0 | 1 |
| 1 |1 |1 | X |
+-------+--+--+-------+
Set (S = 1, R = 0): Q = 1
Reset (S = 0, R = 1): Q = 0
Hold (S = 0, R = 0): Q = Q, previous, the latch holds its previous value.
Invalid (S = 1, R = 1): Q = X, avoid this state as it leads to undefined behavior.
Why This Circuit Acts as an SR Latch?
The feedback connections in the circuit ensure that the output Q is stable and maintains its state until the inputs S or R are changed. This behavior is characteristic of an SR latch, which is a fundamental memory element in digital circuits.
Practically it is troublesome to source three different gates as three IC chips will be need. Practically only the universal gates are used.
The 74LS02 chip contains four 2-input NOR gates. The SR latch can be implemented using two NOR gates.
R----\ \
)NOR1)O--+--- Q
+-/ / |
| |
+------------)-+
| |
+-----------+ |
| |
+-\ \ |
)NOR2)O-----+- Q'
S----/ /
|S|R| Q | Q'|
-------------
|0|0| Hold |
|0|1| 0 | 1 |
|1|0| 1 | 0 |
|1|1|Invalid|
+-+-+-+-------+-----------+
|Q|S|R|Q(t+1) | Operation |
+-+-+-+-------+-----------+
|0|0|0| 0 | Hold |
|0|0|1| 0 | Reset |
|0|1|0| 1 | Set |
|0|1|1| X | Illegal |
|1|0|0| 1 | Hold |
|1|0|1| 0 | Reset |
|1|1|0| 1 | Set |
|1|1|1| X | Illegal |
+-+-+-+-------+-----------+
The 74LS00 chip contains four 2-input NAND gates. The SR latch can be implemented using two NAND gates.
S'---| \
|NAND1)O--+---- Q
+-| / |
| |
+------------)--+
| |
+-----------+ |
| |
+-| \ |
|NAND2)O-----+- Q'
R'---| /
+-+--+--+-------+
|Q|S'|R'|Q(t+1) |
+-+--+--+-------+
|0|0 |0 | X | Illegal
|0|0 |1 | 1 | Set
|0|1 |0 | 0 | Reset
|0|1 |1 | 0 | Hold
|1|0 |0 | X | Illegal
|1|0 |1 | 1 | Set
|1|1 |0 | 0 | Reset
|1|1 |1 | 1 | Hold
+-+--+--+-------+
The operation of NAND based SR latch is different from normal SR latch in that the inputs are inverted. Here S=0, R=1 means set operation and S=1, R=0 means reset operation. NAND gate implementation is useful as it allows us to add an ENABLE input.
The SR latch will perform its operation only when ENABLE input is active.
A major limitation of the basic SR latch is that inputs can change at any time, leading to unintended changes in output. To address this, a Gated SR latch introduces an Enable (En) signal. The latch responds to S and R only when En = 1, preventing accidental state changes.
S-----| \ X
|NAND)O---| \
+-| / |NAND1)O--+---- Q
| +-| / |
| | |
| +------------)--+
En--+ | |
| +-----------+ |
| | |
| +-| \ |
+-| \ |NAND2)O-----+- Q'
|NAND)O---| /
R-----| / Y
Logic diagram of gated SR latch
The two additional NAND gates at input control when to pass S and R signals to SR latch. The equation of top-left NAND gate is
X = (S.En)'
If En=1, it reduces to X = S'. S is applied to the latch after inversion.
If En=0, it reduces to X=1. The set signal is inactivated, and it does not reach SR latch.
Similarly, Reset input is also prevented from reaching SR latch when En=0.
Characteristic table of gate SR latch.
+--+-+--+--+-------+
|En|Q|S'|R'|Q(t+1) |
+--+-+--+--+-------+
|1 |0|0 |0 | X | Illegal
|1 |0|0 |1 | 1 | Set
|1 |0|1 |0 | 0 | Reset
|1 |0|1 |1 | 0 | Hold
|1 |1|0 |0 | X | Illegal
|1 |1|0 |1 | 1 | Set
|1 |1|1 |0 | 0 | Reset
|1 |1|1 |1 | 1 | Hold
|0 |Q|X |X | Q | Hold
+--+-+--+--+-------+
The SR latch’s invalid state (S=1, R=1) can be problematic in practical applications. To overcome this, the D (Data) latch ensures that S and R are never activated simultaneously:
D = 1: Acts as Set (S=1, R=0)
D = 0: Acts as Reset (S=0, R=1)
The Enable (En) input ensures that changes occur only when required.
This latch is widely used in data storage applications as it stores the input D when En = 1.
D -+-----| \ X
| |NAND)O---| \
| +-| / |NAND1)O--+---- Q
| | +-| / |
| | | |
| | +------------)-+
En--)--+ | |
| | +-----------+ |
| | | |
| | +-| \ |
| +-| \ |NAND2)O-----+- Q'
| |\ |NAND)O---| /
+-| O-| / Y
|/
Logic diagram of gated D flip-flop
Characteristic table of gated D flip-flop
+-+-+-+-------+-----------+
|E|Q|D|Q(t+1) | Operation |
+-+-+-+-------+-----------+
|0|0|0| 0 | Hold |
|0|0|1| 0 | Hold |
|0|1|0| 1 | Hold |
|0|1|1| 1 | Hold |
|1|0|0| 0 | Reset |
|1|0|1| 1 | Set |
|1|1|0| 0 | Reset |
|1|1|1| 1 | Set |
+-+-+-+-------+-----------+
While the D latch works well, it still allows changes whenever En = 1. To prevent this, a D flip-flop is introduced using an edge detection mechanism:
The D flip-flop stores data only on the rising edge (or falling edge) of a clock signal (Clk).
This feature makes D flip-flop suitable for synchronous circuits, where precise timing is crucial.
|\
Clk --+-| O--| \
| |/ |AND)-- En
+------| /
Clk: ________|‾‾‾‾‾‾‾‾‾‾|__________|‾‾‾‾‾‾‾
Clk': ‾‾‾‾‾‾‾‾‾‾|__________|‾‾‾‾‾‾‾‾‾‾|_____
En: ________|‾|___________________|‾|_____
Edge detection circuit
D -----------------+-----| \
| |NAND)O---| \
| +-| / |NAND1)O--+---- Q
| | +-| / |
|\ | | | |
Clk -+--| O---| \ | | +------------)-+
| |/ |AND)---)--+ | |
+--------| / | | +-----------+ |
| | | |
| | +-| \ |
| +-| \ |NAND2)O-----+- Q'
| |\ |NAND)O---| /
+-| O-| /
|/
D Flip-flop with edge detection
Here is the characteristics table of D flip-flop.
+--+-+-+-------+-----------+
|En|Q|D|Q(t+1) | Operation |
+--+-+-+-------+-----------+
|X |Q|X| Q | Hold | Flipflop works
|^ |0|0| 0 | Reset | only on
|^ |0|1| 1 | Set | positive edge
|^ |1|0| 0 | Reset | of Enable
|^ |1|1| 1 | Set | input
+--+-+-+-------+-----------+
Here is the block diagram of D flip-flop.
+-------+
D ---| D |
| Flip |
Clk ---|> Flop |
+-------+
SR latch has an illegal input as Set and Reset operations cannot be performed simultaneously. To avoid this condition JK latch is invented. It has well defined behavior if Set and Reset are simultaneously active. In that case, latch will TOGGLE its state. The toggle operation is useful in building counter and frequency dividers. Here is the logic diagram of JK flip flop.
+----------------------------------+
| |
+-| \ X |
J -----|NAND)O---| \ |
+-| / |NAND1)O--+-------+-----)-- Q
| +-| / | | |
|\ | | | | |
Clk --+--| O---| \ | +------------)--+ | |
| |/ |AND)--+ | | | |
+--------| / | +-----------+ | | |
| | | | |
| +-| \ | | |
+-| \ |NAND2)O------+----)---+--- Q'
K -----|NAND)O---| / |
+-| / Y |
| |
+-----------------------------+
Logic diagram of JK flip flop
+--+-+-+-------+-----------+
|En|J|K|Q(t+1) | Operation |
+--+-+-+-------+-----------+
|X |X|X| Q | Hold |
|^ |0|0| Q | Hold |
|^ |0|1| 1 | Reset |
|^ |1|0| 0 | Set |
|^ |1|1| Q' | Toggle |
+--+-+-+-------+-----------+
A T (Toggle) flip-flop is derived from a JK flip-flop by setting J = K = T:
T = 0 → Holds previous state.
T = 1 → Toggles output.
This flip-flop is commonly used in frequency division and binary counters.
+-----------------------------------+
| |
+--| \ X |
T --+----|NAND)O---| \ |
| +-| / |NAND1)O--+-------+-----)-- Q
| | +-| / | | |
|\ | | | | | |
Clk --+--| O---| \ | | +------------)--+ | |
| |/ |AND)--)-+ | | | |
+--------| / | | +-----------+ | | |
| | | | | |
| | +-| \ | | |
| +-| \ |NAND2)O------+----)---+--- Q'
+----|NAND)O---| / |
+-| / Y |
| |
+-----------------------------+
Logic diagram of T flip flop
Here is the characteristic table of T flip flop.
+-+-------+-----------+
|T|Q(t+1) | Operation |
+-+-------+-----------+
|0| Q(t) | Hold |
|1| Q'(t) | Toggle |
+-+-------+-----------+
All transitions take place on edge of the clock.