To implement and observe the working of the CD4026 Decade Counter by interfacing it with a 7-segment display on a breadboard using a digital trainer. The experiment demonstrates how the IC counts from 0 to 9 with a clock pulse and shows the value on the 7-segment display.
CD4026 IC
Common cathode 7-segment display
Breadboard
Digital Trainer Kit (with 5V, clock generator, and buttons)
Jumper wires
Connect Pin 16 (VDD) of CD4026 to +5V supply.
Connect Pin 8 (VSS) to GND.
Connect Pin 1 (CLOCK) to a push-button (momentary switch) on the trainer kit.
Make sure the button sends a positive edge pulse when pressed.
Connect Pin 2 (CLOCK INHIBIT) to GND (LOW), to allow clock pulses.
Connect Pin 3 (DISPLAY ENABLE IN) to a switch, to turn on and turn off the display.
Connect Pin 15 (RESET) to another switch, wired such that pressing it pulls the pin HIGH, to reset the count.
Use a common cathode 7-segment display.
Connect display segments a to g to Pins 10, 12, 13, 9, 11, 6, 7 respectively from the CD4026.
You may place 330Ω resistors in series with each segment for current limiting (optional, for LED protection).
Apply the clock: The display should increment 0 → 1 → 2 … up to 9.
After 9, the counter rolls over to 0 again.
Press the reset button to bring the count back to 0.
+--------+-----------+
| Clock | Displayed |
| Pulses | Number |
+--------+-----------+
| 0 | 0 |
| 1 | 1 |
| 2 | 2 |
| 3 | 3 |
| 4 | 4 |
| 5 | 5 |
| 6 | 6 |
| 7 | 7 |
| 8 | 8 |
| 9 | 9 |
+--------+-----------+
The CD4026 counter successfully counted from 0 to 9 and displayed each digit on the 7-segment display with each clock pulse. The RESET function also worked as expected.
Ensure all power connections are made correctly before powering ON.
Use a common cathode display only.
Don’t leave unused input pins floating—tie them to GND or VDD as needed.
Use resistors for segments if brightness is too high.
.-------u-------.
CLOCK | 1 o 16 | VDD
CLOCK INHIB | 2 15 | RESET
DISPLAY ENI | 3 14 | UNGATED "C" SEG OUT
DISPLAY ENO | 4 CD4026 13 | c
CARRY OUT | 5 12 | b
f | 6 11 | e
g | 7 10 | a
VSS | 8 9 | d
'---------------'
a
+-----+
f | g | b
+-----+
e | | c
+-----+
d
Here's a breakdown of the pin configuration:
Pin 1 (CLK): Clock input, the counting occurs on the rising edge of this signal.
Pin 2 (INH): Clock inhibit, typically grounded to enable the clock function.
Pin 3 (Display Enable Input): Enable input, connected to +5V (high) to enable the output pins (Out A to Out G).
Pin 4 (Display Enable Output): Enable output, an output pin that remains high and is used when cascading multiple CD4026 ICs.
Pin 5 (Carry Over): Divide by 10 output (carry over), used for cascading multiple ICs.
Pins 6-13 (7-Segment outputs a-g): Decoded output pins, connected to a 7-segment display.
Pin 8 (GND): Ground, should be connected to the ground of the circuit.
Pin 14 (Ungated C Segment): Ungated C segment pin, rarely used unless division is required.
Pin 15 (RESET): Reset input, when made high (+5V) will reset the count to 0.
Pin 16 (VCC): Power supply, typically +5V.