To design and implement an SR latch using:
NAND gates (74LS00 chip)
NOR gates (74LS02 chip)
Verify the functionality of the SR latch by constructing its truth table and observing its behavior.
74LS00 IC (Quad 2-input NAND gates)
74LS02 IC (Quad 2-input NOR gates)
Breadboard
Connecting wires
Power supply (5V)
LEDs (to observe outputs)
Push buttons (for S and R inputs)
An SR latch is a basic memory element that can store one bit of information. It has two inputs:
S (Set): Sets the output Q to 1.
R (Reset): Resets the output Q to 0.
The latch has two outputs:
Q: Represents the stored bit.
Q': The complement of Q.
The basic implementation of an SR latch using AND, OR and NOT is presented. Let's break it down step by step to understand how it works as an SR latch.
+-----------------+
| |
+-\ \ |
)OR)--+ Y |
S --/ / | |
| |
+-| \ |
|\ |AND)--+-- Q
R -----| O---| /
|/ Z
The latch "remembers" its state (Q) until it is changed by the inputs.
The circuit consists of:
An OR gate for the Set (S) input.
A NOT gate to complement the Reset (R) input.
An AND gate for inverted Reset (R) input.
There is a feedback connection from the output Q to the input of the OR gate.
Here is the stepwise demo of how the SR latch circuit works:
Assume the initial state is Q = 0. (We can equally suppose Q = 1).
S = 1 is applied to the OR gate.
The OR gate output Y is 1, since OR gate output is 1 if any inputs is 1.
R = 0 is applied to NOT gate input. Its output Z is 1.
Both inputs of AND gate are 1 so its output Q is set to 1.
This is the set operation and Q is set to 1.
When both S = 0 and R = 0, the circuit maintains its previous state.
The OR gate output stays at 1.
Both AND gate inputs are 1 and its output Q stays 1.
The feedback connection ensure that the outputs Q remain the same.
This is the hold operation.
R = 1 is applied to the AND gate.
The NOT gate output Z is 0.
The AND gate output is 0, since one of its inputs is 0.
This 0 becomes the new value of Q.
The feedback ensures that Q = 0 is stable until the inputs change.
This is the reset operation
With both S = 0 and R = 0, the circuit maintains its current state.
The feedback connections ensure that the outputs Q remain 0.
If both S = 1 and R = 1 are applied simultaneously, the circuit enters an illegal state.
The OR gate outputs 1, and the AND gate outputs 0. However, this state is not permitted.
Applying Set and Reset at the same time does not make sense.
This state is undefined and should be avoided.
+-------+--+--++-------+
|Q prev |S |R |Q next |
+-------+--+--+-------+
| 0 |0 |0 | 0 |
| 0 |0 |1 | 0 |
| 0 |1 |0 | 1 |
| 0 |1 |1 | X |
| 1 |0 |0 | 1 |
| 1 |0 |1 | 0 |
| 1 |1 |0 | 1 |
| 1 |1 |1 | X |
+-------+--+--+-------+
Set (S = 1, R = 0): Q = 1
Reset (S = 0, R = 1): Q = 0
Hold (S = 0, R = 0): Q = Q, previous, the latch holds its previous value.
Invalid (S = 1, R = 1): Q = X, avoid this state as it leads to undefined behavior.
Why This Circuit Acts as an SR Latch?
The feedback connections in the circuit ensure that the output Q is stable and maintains its state until the inputs S or R are changed. This behavior is characteristic of an SR latch, which is a fundamental memory element in digital circuits.
Practically it is troublesome to source three different gates as three IC chips will be need. Practically only the universal gates are used.
The 74LS02 chip contains four 2-input NOR gates. The SR latch can be implemented using two NOR gates.
Logic Diagram (NOR-based SR Latch):
R----\ \
)NOR1)O---+--- Q
+-/ / |
| |
+-----------|--+
| |
+-----------+ |
| |
+-\ \ |
)NOR2)O-----+- Q'
S----/ /
Truth Table (NOR-based SR Latch):
|S|R| Q | Q'|
-------------
|0|0| Hold |
|0|1| 0 | 1 |
|1|0| 1 | 0 |
|1|1|Invalid|
The 74LS00 chip contains four 2-input NAND gates. The SR latch can be implemented using two NAND gates.
S'---| \
|NAND1)O--+---- Q
+-| / |
| |
+-----------|--+
| |
+-----------+ |
| |
+-| \ |
|NAND2)O-----+- Q'
R'---| /
|S'|R'| Q | Q'|
-------------
|0 |0 |Invalid|
|0 |1 | 1 | 0 |
|1 |0 | 0 | 1 |
|1 |1 | Hold |
Circuit Setup:
Connect VCC (pin 14) and GND (pin 7) of the 74LS00 IC to the power supply.
Use two NAND gates from the 74LS00 IC to implement the SR latch.
Connect the inputs (S and R) to push buttons.
Connect the outputs (Q and Q') to LEDs.
Testing:
Apply different combinations of S and R inputs and observe the outputs Q and Q'.
Record the results in the truth table.
Circuit Setup:
Connect VCC (pin 14) and GND (pin 7) of the 74LS02 IC to the power supply.
Use two NOR gates from the 74LS02 IC to implement the SR latch.
Connect the inputs (S and R) to push buttons.
Connect the outputs (Q and Q') to LEDs.
Testing:
Apply different combinations of S and R inputs and observe the outputs Q and Q'.
Record the results in the truth table.
For the NAND-based SR latch:
When S = 1 and R = 1, the latch holds its previous state.
When S = 1 and R = 0, Q = 1 and Q' = 0.
When S = 0 and R = 1, Q = 0 and Q' = 1.
When S = 0 and R = 0, the output is invalid.
For the NOR-based SR latch:
When S = 0 and R = 0, the latch holds its previous state.
When S = 0 and R = 1, Q = 0 and Q' = 1.
When S = 1 and R = 0, Q = 1 and Q' = 0.
When S = 1 and R = 1, the output is invalid.
Write VHDL code for RS-Latch architecture and test bench to simulate its operation. Include code and output waveforms in your lab reports and discuss how they simulate SR operation.
The SR latch is a fundamental memory element that can store one bit of information.
The NAND-based SR latch is active-low, while the NOR-based SR latch is active-high.
The invalid state occurs when both inputs are active simultaneously, which should be avoided in practical applications.
Ensure proper connections to avoid short circuits.
Use resistors with LEDs to prevent excessive current flow.
Double-check the pin configuration of the ICs before connecting.
What is the difference between a NAND-based and NOR-based SR latch?
Why is the state S = 0, R = 0 invalid in a NAND-based SR latch?
How can you modify the circuit to avoid the invalid state?
This lab manual provides a step-by-step guide to implementing and analyzing SR latches using NAND and NOR gates. Students are encouraged to explore further by designing other sequential circuits using these basic building blocks.