Complex Computing Problem

Design and Implementation of a 4-bit ALU using VHDL

Problem Statement:

Design a 4-bit Arithmetic Logic Unit (ALU) using VHDL that supports the following operations:

• Arithmetic: Addition, Subtraction

• Logical: AND, OR, XOR

• Shift: Logical Left, Logical Right

• Comparison: Zero, Equality

The ALU should be implemented in VHDL and then verified using a VHDL testbench. Students must demonstrate correct timing simulation, resource analysis, and documentation of the design process.

Design Requirements:

• Input: Two 4-bit operands and a 3-bit opcode

• Output: 4-bit result, carry/borrow flag, zero flag

• VHDL coding standards must be followed

• Testbench must simulate all operations

Introduction

An Arithmetic Logic Unit (ALU) is a fundamental component in digital computing system. It performs arithmetic and logical operations on binary data, serving as the core of central processing units (CPUs). Industrial applications rely on optimized ALU designs for quick data processing in areas such as telecommunications, automation, medical devices, and high-performance computing.

For computer science students, designing an ALU is a vital step in understanding how hardware processes data at the bit level. It reinforces concepts in digital logic, binary arithmetic, modular design, and hardware description languages such as VHDL. By building a 4-bit ALU, students gain hands-on experience with simulation, and performance evaluation—skills that are critical for careers in digital system design, FPGA development, and embedded engineering.

Deliverables:

• VHDL source files and testbench source files

• Simulation results screenshots

• Design document and user manual

Submission Deadline: 16-May-2025