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Digital Logic Design Lab
1 Lab Equipment
2 Logic Gates
3 Universal Gate Logic
3 Boolean Function
4 DeMUX n Decoder
5 Binary Adder
6 ROM from DRL
7 SR Latch
8 Design with D-FF
9 JK FF
10 Shift Registers
11 Counters
12 Decade Counter
13 Install HDL
14 VHDL Intro
15 VHDL MUX
Lab Report Guidelines
Digital Logic Design
DLD Outline
Presentations
Number System
Boolean Algebra
Karnaugh Map
TebularMethod
Past Exams
SR Latch Working
Sequential Analysis
Sequential Design
CCP CPU
Data Science Lab
Python basics
Tuples and lists
Classes and objects
Pandas and dataframes
Data Statistics
Webscraping using BFS
Frequency Analysis
Regression model
Naive Baysian
SQL Database
kNN and Decision Tree
Good Deeds
Counters
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